The present invention relates to an information processing apparatus of the type in which instructions are executed by a pipeline control method, by which instructions are executed at high speed.
A format of a non-register type instruction, typically a branch instruction, is shown in FIG. 1A. In the figure, OP represents an operation code (OP code) of an instruction. Mask field M1 indicates a branch condition. An address of a target instruction to be branched is obtained from a sum of (X2)+(B2)+D2, wherein ( ) represents the contents of the register. A format of a register type (RR type) instruction is shown in FIG. 1B. In the figure, OP represents an operation code of an instruction. The first operand is held in a register designated by R1 in a general purpose register or a floating-point register, while the second operand is held in a register designated by R2 in the general purpose register or a floating-point register. A register type instruction is characterized by the fact that both operands are held in registers. In the present application, a register type instruction or a first type instruction is defined as an instruction of the type in which all of the operands necessary to execute such instruction are stored in certain registers in the general purpose register or the floating-point register and a non-register type instruction or a second type instruction is defined as an instruction of the type in which at least one of the operands necessary to execute such instruction is held in the memory.
FIG. 2A illustrates the conventional operation of a branch instruction using a pipeline control method. D, A, L, E and P in FIG. 2A each represent a stage in pipelining operation. A different instruction is inputted into a pipeline one cycle after another, and a plurality of instructions can be processed in parallel at a time. In FIG. 2A, instructions 0 to 3 represent a register type instruction, instruction 4 represents a branch instruction which is a non-register type instruction, and instruction 5 represents a target instruction to be branched.
Stage D decodes an instruction, reads an index register (X2) and a base register (B2) to perform a logical operation (X2)+(B2)+D2 on the basis of the read contents of the registers, and obtains an address of a storage unit from which data (operand) to be executed is read out. Stages A and L access the storage unit on the basis of the obtained address. Stage E executes the read operand data. Stage P writes the executed result in registers.
Conventionally, fetching a target instruction 5 to be branched has been executed at stages D, A and L of the branch instruction 4. The target instruction 5 to be branched is loaded into an instruction buffer at the E stage following the L stage of the branch instruction 4. As a result, as shown in FIG. 2A, if the stage E is considered, the stage E of the target instruction 5 to be branched starts 3 cycles after stage E of the branch instruction 4 so that the operation performance of the branch instruction is poor.
Further, since decoding of the instruction which follows a register type instruction like the instruction 0, 1, 2 or 3 is possible only after completion of the D stage of the register type instruction, there is a problem that it takes a long time to execute a plurality of instructions which includes register type instructions.
A related information processing apparatus of this type is disclosed, for example, in JP-A- No. 59-94444.